Intel's Breakthrough Tri-Gate 3-D Transistor Design for Ivy Bridge Explained

Intel on May 4 announced that it is ready to put Tri-Gate transistors with a three-dimensional structure into high volume production with its 22-nanometer (nm) "Ivy Bridge" architecture.

Tri-Gate 3-D transistor design, first disclosed by Intel in 2002, represent a departure from the two-dimensional planar transistor structure so far in use.

The Intel breakthrough comes as the increasingly dense packing of transistors on silicon chips neared physical limits that threatened to derail Moore's Law, which states that roughly every 2 years transistor density will double, while increasing functionality and performance and decreasing costs.

Moore's law has been the basic business model for the semiconductor industry for more than 40 years.

"Intel's scientists and engineers have once again reinvented the transistor, this time utilizing the third dimension," said Intel President and CEO Paul Otellini. "Amazing, world-shaping devices will be created from this capability as we advance Moore's Law into new realms."

Tri-Gate Transistors: Unprecedented Power Savings and Performance Gains

Intel's 3-D Tri-Gate transistors enable chips to operate at lower voltage with lower leakage, improving performance and energy efficiency compared to previous state-of-the-art transistors.

The 22nm 3-D Tri-Gate transistors provide up to 37 percent performance increase at low voltage versus Intel's 32nm planar transistors. Alternatively, they consume less than half the power when at the same performance.

The performance gains and power savings go further than simply keeping up with Moore's Law, says an Intel official.

"The low-voltage and low-power benefits far exceed what we typically see from one process generation to the next."

The 3-D Tri-Gate transistors are a reinvention of the transistor. The traditional "flat" two-dimensional planar gate is replaced with an incredibly thin three-dimensional silicon fin that rises up vertically from the silicon substrate. Control of current is accomplished by implementing a gate on each of the three sides of the fin – two on each side and one across the top -- rather than just one on top, as is the case with the 2-D planar transistor. The additional control enables as much transistor current flowing as possible when the transistor is in the "on" state (for performance), and as close to zero as possible when it is in the "off" state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance).

This video will help you understand the 22nm Ivy Bridge architecture as well as 3-D Tri-Gate transistors.